Prior art approaches to inter-chip communication utilize unidirectional signal flow on either a point to point interconnect, or a shared bus. For systems in which the electrical length of the interconnect is significant in relation to the edge rate or fundamental frequency of the signals traversing them, and operation at the highest possible speeds is desired, the interconnect medium consists of controlled impedance traces terminated in their characteristic impedance. The goal of these interconnect designs is to obtain the optimum combination of bandwidth, number of wires, power, and cost. The prior art schemes require many wires (e.g., one per signal plus an additional wire for each bidirectional signal) with their corresponding termination resistors in order to achieve the highest possible bandwidth. The termination resistors are used to prevent signal reflection back to the sender, reducing the amount of noise present on the wire.
Current and next generation supercomputers frequently utilize an active backplane with routing components forming a communications mesh. Point-to-point interconnects are used between components on the backplane. FIG. 1 shows a typical prior art approach used in recently developed routers where the links between routers are double terminated; the driver 11 is matched to the impedance of the line Z.sub.0, and the line 13 is parallel terminated using a Thevenin equivalent termination 15. The scheme shown in FIG. 1 is described in detail by E. Reese, et al., "A Phase-Tolerant 3.8GB/s Data-Communication Router for a Multiprocessor Supercomputer Backplane", IEEE Solid-State Circuits Conference, February 1994.
Two goals for future backplanes are to reduce the total number of wires, and remove the termination resistors from the board. One way to reduce the total number of wires is to run the I/O buffers faster than the core circuits of the routing component. For example, with the core of the routing component operating at 200 MHz, reducing the number of pins per port by half would mean that the I/O buffers would need to operate at 400 MHz. This would require two separate clocks for the component, and these clocks would need to be phase locked. Distributing a 400 MHz clock across a system consisting of several thousand processing nodes would not be a simple task. Synthesizing this clock on chip would prove equally challenging.
Another approach would be to increase the information density on the wires by using a form of multi-valued logic, rather than binary. This would be attractive if the latency incurred as a result of encoding and decoding is not excessive, the signal to noise ratio is not degraded, and the gain bandwidth product of the input amplifier is sufficient to handle the smaller swings.
Neither of these approaches addresses the problem of the many on board termination resistors and their associated power consumption. Integration of the terminations on the die forming the integrated circuit would increase the size of the input cell, its corresponding pad capacitance, and the power it consumes. Incorporation of the resistors into the interconnect structure of either the board or the package is a possibility, if there is adequate room in the routing layers, and acceptable resistance tolerances can be achieved, but the power would be unchanged. Termination to a separate supply lowers the power, but the separate supply must be well decoupled in order to maintain a constant termination voltage with respect to the current return path of the driver when many outputs switch simultaneously.